SUPERAID7 - Publications

Publications from the project will be listed here once they have been published.

Below you will find also selected publications describing background work by the project partners.

Public project reports can be found here.

SUPERAID7 Publications

SUPERAID7 poster at the European Nanoelectronics Forum (ENF) 2016, November 23-24, Rome

Publications 2017

T. Al-Ameri, A. Asenov, Vertically Stacked Lateral Si80Ge20 Nanowires Transistors for 5 nm CMOS Applications, in: Proceedings EUROSOI-ULIS 2017

P. Ellinghaus, J. Weinbub, M. Nedjalkov, S. Selberherr, Analysis of Lense-governed Wigner Signed Particle Quantum Dynamics, Phys. Status Solidi RRL 11 (2017) 1700102

Z. Zeng, F. Triozon, S. Barraud, Y.-M. Niquet, A Simple Interpolation Model for the Carrier Mobility in Trigate and Gate-All-Around Silicon NWFETs, IEEE, Trans. Electr. Dev. 64 (2017) 2485

Publications 2016

T. Al-Ameri, V. Georgiev, F.-A. Lema, T. Sadi, X. Wang, E. Towie, C. Riddet, C. Alexander, A. Asenov, Impact of Strain on the Performance of Si Nanowires Transistors at the Scaling Limit: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study, in: Proceedings of 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016), p. 213   Download

S. Barraud et al., Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain, in: Proceedings International Electron Devices Meeting (IEDM) 2016

L. Bourdet, J. Li, J. Pelloux-Prayer, F. Triozon, M. Casse, S. Barraud, S. Martinie, D. Rideau, Y. Niquet, High and Low-field Contact Resistances in Trigate Devices in a Non-Equilibrium Green´s Functions Framework, in: Proceedings of 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016), p. 291   Download

O. Rozeau et al., NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, in: Proceedings International Electron Devices Meeting (IEDM) 2016

T. Sadi, E. Towie, M. Nedjalkov, C. Riddet, C. Alexander, L. Wang, V. Georgiev, A. Brown, C. Millar, A. Asenov, One-Dimensional Multi-Subband Monte Carlo Simulation of Charge Transport in Si Nanowire Transistors, in: Proceedings of 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016), p. 23   Download

L. Wang, B. Cheng, P. Asenov, A. Pender, D. Reid, F. Adamu-Lema, C. Millar, A. Asenov, TCAD Proven Compact Modelling Re-centering Technology for Early 0.x PDKs, in: Proceedings of 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016), p. 157   Download

Z. Zeng, F. Triozon, Y. Niquet, S. Barraud, Size-dependent Carrier Mobilities in Rectangular Silicon Nanowire Devices, in: Proceedings of 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016), p. 257   Download

Z. Zeng, F. Triozon, Y. Niquet, Carrier Scattering by Workfunction Fluctuations and Interface Dipoles in high-κ/Metal Gate Stacks, in: Proceedings of 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2016), p. 369   Download
 

Publications on Partners' Background Work

2016

T. Al-Ameri, V.P. Georgiev, F. Adamu-Lema, X. Wang, A. Asenov, Influence of Quantum Confinement Effects and Device Electrostatic Driven Performance in Ultra-Scaled SixGe1-x Nanowire Transistors, in: Proceedings of 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), IEEE, 2016, pp. 234

A. Asenov, Y. Wang, B. Cheng, X. Wang, P. Asenov, T. Al-Ameri, V.P. Georgiev, Nanowire Transistor Solutions for 5 nm and Beyond, in: Proceedings of 17th International Symposium on Quality Electronic Design (ISQED), IEEE, 2016, pp. 269

E. Baer, J. Niess, Equipment Simulation for Studying the Growth Rate and its Uniformity of Oxide Layers Deposited by Plasma-Enhanced Oxidation, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2016 (SISPAD 2016), p. 137     Download

E. Baer, A. Burenkov, P. Evanschitzky, J. Lorenz, Simulation of Process Variations in FinFET Transistor Patterning, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2016 (SISPAD 2016), p. 299     Download

A. Burenkov, J. Lorenz, Simulation of Thermo-mechanical Effect in Bulk-silicon FinFETs, Materials Science in Semiconductor Processing 42 (2016) 242

L. Wang, T. Sadi, M. Nedjalkov, A. R. Brown, C. Alexander, B. Cheng, C. Millar, A. Asenov, Simulation Analysis of the Electro-thermal Performance of SOI FinFETs, in: Proc. of 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), IEEE, 2016, pp. 56

X. Wang, D. Reid, L. Wang, C. Millar, A. Burenkov, P. Evanschitzky, E. Bär, J. Lorenz, A. Asenov, Process Informed Accurate Compact Modelling of 14-nm FinFET Variability and Application to Statistical 6T-SRAM Simulations, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2016 (SISPAD 2016), p. 303     Download


2015


E. Baer, P. Evanschitzky, J. Lorenz, F. Roger, R. Minixhofer, L. Filipovic, R.L. de Orio, S. Selberherr, Coupled Simulation to Determine the Impact of across Wafer Variations in Oxide PECVD on Electrical and Reliability Parameters of Through-silicon Vias, Microelectronic Engineering 137 (2015) 141

S. Barraud, M. Cassé, L. Gaben, P. Nguyen, J.M. Hartmann, M.P. Samson, V. Maffini-Alvaro, C. Tabone, C. Vizioz, C. Arvet, P. Pimenta-Barros, F. Glowacki, N. Bernier, O. Rozeau, M.A. Jaud, S. Martinie, J. Laccord, F. Allain, B. De Salvo, and M. Vinet, “Opportunities and challenges of nanowire-based CMOS technologies”, S3S conference, 2015

A. Burenkov, J. Lorenz, Y. Spiegel, F. Torregrosa, Simulation of Plasma Immersion Ion Implantation into Silicon, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2015 (SISPAD 2015), p. 218  Download

L. Filipovic, A.P. Singulani, F. Roger, S. Carniello, S. Selberherr, Intrinsic Stress Analysis of Tungsten-lined open TSVs, Microelectr. Reliab. 55 (2015) 1843

L. Gaben, S. Barraud, M.-A. Jaud, S. Martinie, O. Rozeau, J. Lacord, G. Hiblot, S. Monfray, F. Boeuf, T. Skotnicki, F. Balestra, M. Vinet, “Stacked-Nanowire and FinFET transistors: guideline for the 7nm node”, SSDM conference, 2015

L. Gaben, S. Barraud, P. Pimenta-Barros, Y. Morand, J. Pradelles, M.-P. Samson, B. Previtali, P. Besson, F. Allain, S. Monfray, F. Boeuf, T. Skotnicki, F. Balestra, M. Vinet, “Omega-Gate nanowire transistors realized by sidewall image transfer patterning: 35nm channel pitch and opportunities for stacked-Nanowires architectures”, SSDM conference, 2015

R. Nagy, A. Burenkov, J. Lorenz, Numerical Evaluation of the ITRS Transistor Scaling, J. Comput. Electron. 14 (2015) 192

J. Pelloux-Prayer, M. Cassé, F. Triozon, S. Barraud, Y.-M. Niquet, J.-L. Rouvière, O. Faynot, G. Reimbold, “strain effect on mobility in nanowire MOSFETs down to 10nm width: geometrical effects and piezoresistive model”, ESSDERC conference, 2015

F. Roger, A. Singulani, S. Carniello, L. Filipovic, S. Selberherr, Global Statistical Methodology for the Analysis of Equipment Parameter Effects on TSV Formation, in: Proceedings VARI Conference 2015, p. 39

L. Wang, A. R. Brown, M. Nedjalkov, C. Alexander, B. Cheng, C. Millar, A. Asenov, Impact of Self-Heating on the Statistical Variability in Bulk and SOI FinFETs, IEEE Trans. Electr. Dev. 62 (2015) 2106

L. Wang, T. Sadi, M. Nedjalkov, A. R. Brown, C. Alexander, B. Cheng, C. Millar, A. Asenov. An Advanced Electro-Thermal Simulation Methodology For Nanoscale Device, in: Proceedings of IEEE 2015 International Workshop on Computational Electronics (IWCE 2015), p. 1

L. Wang, A. R. Brown, M. Nedjalkov, C. Alexander, B. Cheng, C. Millar, A. Asenov, 3D Electro-Thermal Simulations of Bulk FinFETs with Statistical Variations, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2015 (SISPAD 2015), p. 112  Download

X. Wang, D. Reid, L. Wang, A. Burenkov, C. Millar, J. Lorenz, A. Asenov, Hierarchical Variability-Aware Compact Models of 20nm Bulk CMOS,in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2015 (SISPAD 2015), p. 325  Download

2014

S.M. Amoroso, L. Gerrer, M. Nedjalkov, R. Hussin, C. Alexander, A. Asenov, Modeling Carrier Mobility in Nano-MOSFETs in the Presence of Discrete Trapped Charges: Accuracy and Issues, IEEE Trans. Electr. Dev. 61 (2014) 1292

A. Burenkov, J. Lorenz, Y. Spiegel, F. Torregrosa, Simulation of AsH3 Plasma Immersion Ion Implantation into Silicon, in: Proceedings International Conference on Ion Implantation Technology (IIT) 2014

L. Filipovic, R.L. de Orio, S. Selberherr, Effects of Sidewall Scallops on the Performance and Reliability of Filled Copper and Open Tungsten TSVs, in: Proc. IEEE 21st International Symposium on the Physical and Failure Analysis of Integrated Ciruits (IPFA) 2014, p. 321

L. Filipovic, R.L. de Orio, S. Selberherr, A. Singulani, F. Roger, R. Minixhofer, Effects of Sidewall Scallops on Open Tungsten TSVs, Proceedings International Relaibility Physics Symposium (IRPS) 2014

L. Filipovic, R.L. de Orio, S. Selberherr, Process and Reliability of SF6/O2 Plasma Etched Copper TSVs, Proceedings EuroSimE 2014

L. Filipovic, F. Rudolf, E. Baer, P. Evanschitzky, J. Lorenz, F. Roger, A. Singulani, R. Minixhofer, S. Selberherr, Three-Dimensional Simulation for the Reliability and Electrical Performance of Through-Silicon Vias, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2014 (SISPAD 2014), p. 341  Download

L. Filipovic, S. Selberherr, The Effects of Etching and Deposition on the Performance and Stress Evolution of Open Through Silicon Vias, Microelectr. Reliab. 54 (2014) 1953

J. Lorenz, E. Bär, A. Burenkov, P. Evanschitzky, A. Asenov, L. Wang, X. Wang, A.R. Brown, C. Millar, D. Reid, Simultaneous Simulation of Systematic and Stochastic Process Variations, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2014 (SISPAD 2014), p. 289  Download

P. Nguyen, S. Barraud, C. Tabone, L. Gaben, M. Cassé, F. Glowacki, J.-M. Hartmann, M.-P. Samson, V. Maffini-Alvaro, C. Vizioz, N. Bernier, C. Guedj, C. Mounet, O. Rozeau, A. Toffoli, F. Alain, D. Delprat, B. Y. Nguyen, C. Mazuré, O. Faynot, M. Vinet, “Dual-Channel CMOS Co-Integration with Si NFET and Strained-SiGe PFET in Nanowire Device Architecture Featuring Sub-15nm Gate Length”, IEDM conference, 2014

J. Pelloux-Prayer, M. Cassé, S. Barraud, P. Nguyen, M. Koyama, Y.-M. Niquet, F. Triozon, I. Duchemin, A. Abisset, A. Idrissi-Eloudrhiri, S. Martinie, J.-L. Rouvière, H. Iwai, and G. Reimbold, “Study of the piezoresistive properties of NMOS and PMOS Omega-Gate SOI Nanowire transistors: scalability effects and high stress level”, IEDM conference, 2014

L. Wang, A. R. Brown, M. Nedjalkov, C. Alexander, B. Cheng, C. Millar, A. Asenov, 3D Coupled Electro-Thermal Simulations for SOI FinFET with Statistical Variations Including the Fin Shape Dependence of the Thermal Conductivity, 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2014), Guilin, China, Oct. 2014

L. Wang, A. R. Brown, M. Nedjalkov, C. Alexander, B. Cheng, C. Millar, A. Asenov, 3D Coupled Electro-Thermal FinFET Simulations Including the Fin Shape Dependence of the Thermal Conductivity, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2014 (SISPAD 2014), p. 269  Download

L. Wang, A.R. Brown, C. Millar, A. Burenkov, X. Wang, A. Asenov, J. Lorenz, Simulation for Statistical Variability in Realistic 20 nm MOSFET, in: Proceedings of the 15th International Conference on Ultimate Integration on Silicon (ULIS), 2014, p. 5

X. Wang, D. Reid, L. Wang, A. Burenkov, C. Millar, B. Cheng, A. Lange, J. Lorenz, E. Baer, A. Asenov, Variability-Aware Compact Model Strategy for 20-nm Bulk MOSFETs, in: Proceedings of Conference on Simulation of Semiconductor Processes and Devices 2014 (SISPAD 2014), p. 293 Download