233rd Meeting of the Electrochemical Society (ECS Spring Meeting 2018)
May 13-17, 2018, Seattle, United States
An invited presentation will show results from SUPERAID7:
J. Lorenz, Process Variability for Devices at and beyond the 7 nm Node
2017 IEEE International Electron Devices Meeting (IEDM 2017)
December 2-6, 2017 2017 in San Francisco
The following paper reported on results of SUPERADI7:
S. Barraud et al., Performance and Design Considerations for Gate-All-around Stacked-NanoWires FETs
2017 International Conference on Solid State Devices and Materials (SSDM 2017)
September 19-22, 2017, Sendai, Japan
Among others, an invited presentation showed results from SUPERAID7:
S. Barraud et al., Stacked-Wires FETs for Advanced CMOS Scaling
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2017
September 7-9, 2017, Kamakura, Japan
Among others, a plenary presentation showed results from SUPERAID7:
J.-C. Barbé et al., Stacked Nanowires/Nanosheets Gate-All-Around MOSFET from Technology to Design Enablement
2016 IEEE International Electron Devices Meeting (IEDM 2016)
December 3-7, 2016, San Francisco, United States
The following papers reported on results from SUPERAID7:
Paper 7.5 - NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, by O. Rozeau et al.
Paper 17.6 - Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain, by S. Barraud et al.
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2016
(organized by Fraunhofer IISB)
September 6-8, 2016, Nuremberg, Germany
In 6 papers at SISPAD 2016, results of SUPERAID7 were shown, please refer to the SUPERAID7 publications list for further information.
The SISPAD 2016 workshops WS1 (Simulation of Advanced Interconnects) and WS3 (Variability-Aware Design Technology Co-Optimization) were organized in cooperation with SUPERAID7.