SUPERAID7 - Events

SUPERAID7 Workshop
"Process Variations from Equipment Effects to Circuit and Design Impacts"
(linked to ESSDERC/ESSCIRC 2018)

September 3, 2018, Dresden, Germany

Further information and registration

2017 International Conference on Solid State Devices and Materials (SSDM 2017)

September 19-22, 2017, Sendai, Japan

Among others, an invited presentation showed results from SUPERAID7:
S. Barraud et al., Stacked-Wires FETs for Advanced CMOS Scaling

2016 IEEE International Electron Devices Meeting (IEDM 2016)

December 3-7, 2016, San Francisco, United States

The following papers reported on results from SUPERAID7:
Paper 7.5 - NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, by O. Rozeau et al.
Paper 17.6 - Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain, by S. Barraud et al.

International Workshop on Timing Modeling, Organization and Simulation (PATMOS 2016) in conjunction with the European Workshop on CMOS Variability (VARI 2016)

September 21 to 23, 2016, Bremen, Germany

Presentation by J. Lorenz on SUPERAID7